SiPlex™ System-level Heterogeneous Integration Platform

Full-stack high-density SiP solution enables instant collaboration of multiple chips in a single package

SiPlex™ is a next-generation System-in-Package (SiP) platform designed for 5G-Advanced, AI edge, automotive, and wearable markets. It seamlessly integrates bare dies, passive components, and antennas with different processes and functions into a single package through wafer-level high-density redistribution, multi-stage embedded substrates, 2.5D/3D stacking, and Chiplet interfaces. This achieves system-level miniaturization with "performance approaching SoC and flexibility surpassing PCB," enabling customers to complete full-cycle delivery from RTL to mass production within 12 weeks.

YCHIPWAY

Product dimensions：2.0×2.0mm ~ 45×45mm, support ultra-thin and special-shaped customization, suitable for integrated packaging of multi-chip and passive components

Product Application：Wearable devices, consumer electronics, IoT modules, automotive intelligent terminals, portable medical electronics, communication terminals, aerospace miniaturized system modules

detailed introduction

Product Overview

SiPlex™ adopts a "Design-For-SiP" collaborative design flow, compressing traditional board-level systems into a 10 mm × 10 mm package. Core technologies include:

• Ultra-high density RDL (2 µm L/S) with micro bumps at 30 µm pitch;

• 2.5D silicon interposer / 3D TSV vertical interconnects;

• Multi-zone co-fired substrate (ABF+BT hybrid) ensuring 260 °C lead-free reflow;

• Built-in EMI shielding and antenna integration, supporting millimeter-wave AiP;

• Comprehensive signal integrity, power integrity, and thermo-mechanical co-simulation platform.

Product Applications

• 5G/6G smartphone RF front-end modules (FEMiD, PAMiD)

• AR/VR all-in-one sensor-compute-memory fusion SiP

• Automotive high-reliability domain controllers (ASIL-D)

• Ultra-low-power SiP for medical implantable neurostimulators

Technical Features

Heterogeneous Compatibility: Supports logic (5 nm), RF (28 nm), memory (LPDDR5/6), MEMS, and optical sensing bare die co-integration.

Extreme Miniaturization: Package density ≥ 1000 I/O/mm², system volume reduced by 70%, interconnect loss < 0.2 dB/mm @28 GHz.

High Reliability: Compliant with AEC-Q100 Grade 1, MIL-STD-883 mechanical shock, and 1000 h high-temperature/humidity validation; MTTF > 10 kh at 150 °C junction temperature.

DFN/QFN Framework Encapsulatio...

High-reliability, high heat dissipation, high-density general-purpose chip interconnection and packaging integrated solution

LGA Carrier Board Packaging So...

LGA substrates are used in consumer electronics and banking product series such as mobile payments, credit cards, and electronic tags. Ultra-thin LGA chips achieve top-side heat dissipation, optimizing chip performance.