BGA packaging (High-Density Substrate Array Grid Packaging)

High-density interconnect: mainstream packaging solution for high-performance chips

BGA (Ball Grid Array) packaging is a core packaging form for high-end semiconductors. It adopts a bottom solder ball array interconnection structure and possesses core advantages such as high I/O pin density, excellent electrical performance, good heat dissipation, and compact packaging size. It can meet the needs of high-speed signal transmission and high-power device applications, and is widely suitable for high-end chip scenarios such as CPUs, GPUs, 5G communication, automotive domain control, and AI computing power. It is a key packaging technology for the mass production of high-performance integrated circuits.

YCHIPWAY

Product dimensions：2.0×2.0mm ~ 60×60mm, supporting fine-pitch solder balls, high-density pins, suitable for ultra-thin and large-size customized packaging

Product Application：CPU/GPU, FPGA, 5G communication chips, server main control chips, automotive domain controllers, high-end memory, AI computing chips

detailed introduction

Product Overview

BAG-XT® (Board-level Array Grid eXtreme Package) is a substrate-level array grid packaging platform specifically designed for the Chiplet and heterogeneous integration era. By utilizing large-area organic/inorganic composite substrates, micro-bump arrays, and precision RDL redistribution layer technology, BAG-XT® enables parallel interconnection of multiple chiplets (CPU, GPU, IO Die, HBM, etc.) with different process nodes within a single package. It delivers up to 2 TB/s of package-level bandwidth with <0.5 pJ/bit power efficiency, providing a scalable, low-latency, and highly reliable system-in-package foundation for data centers, AI acceleration, and network switching equipment.

Applications

• AI/HPC Servers: Chiplet integration of CPU+GPU+HBM3E

• Network Switch Chips: Co-packaged switching chiplets with high-speed SerDes IO Die

• 5G Base Stations: Heterogeneous integration of RF front-end, digital intermediate frequency, and baseband chiplets

• Vehicle Domain Control: Mixed packaging of MCU, NPU, and functional safety monitoring chiplets

Technical Features

Substrate Scale: Maximum package size 110 mm × 110 mm, accommodating ≥6 chiplets

Interconnect Density: 25 µm micro-bump pitch, 1 µm/1 µm RDL line width/spacing, supporting ≥10-layer RDL stacking

Signal Integrity: Insertion loss <0.35 dB/mm @ 56 GHz, impedance control ±5%

Thermal Management: Integrated embedded microchannel liquid cooling + high-thermal-conductivity TIM, single-package heat dissipation ≥600 W

Reliability: Certified by JEDEC JESD22-A104 (-55°C~150°C, 1000 cycles) and JESD22-A108 HTOL 1000 h

Standards Compliance: Meets UCIe 1.1, JEDEC Wide-IO/HBM3 physical layer specifications, and RoHS 2.0 environmental requirements

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High-density interconnect: mainstream packaging solution for high-performance chips